ISO/IEC 18372:2004

This standard was last reviewed and confirmed in 2018. Therefore this version remains current.

The electronic version of this International Standard can be downloaded from the ISO/IEC Information Technology Task Force (ITTF) web site

Abstract

Preview

The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.

General information

Status
: Published

Publication date
: 2004-12
Edition
: 1

Number of pages
: 405
Technical Committee
: ISO/IEC JTC 1/SC 25 Interconnection of information technology equipment
ICS
:
35.100.30 Network layer

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	Format	Language
std 1 208	PDF on CD

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Life cycle

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Published

ISO/IEC 18372:2004

A standard is reviewed every 5 years
Stage: 90.93 (Confirmed)

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