This standard was last reviewed and confirmed in 2018. Therefore this version remains current.
Defines the address-space maps, the bus transaction sets, and the node's CSRs. Includes the format and content of the configuration ROM on the node providing the parameters necessary to autoconfigure systems with nonprocessor nodes provided by multiple vendors. The annexes provide background for understanding the usage of this CSR Archtecture specification.
Status: PublishedPublication date: 1994-10
Edition: 1Number of pages: 135
Technical Committee: ISO/IEC JTC 1/SC 25 Interconnection of information technology equipment
- ICS :
- 35.160 Microprocessor systems
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|std 1 208|
|std 2 208||Paper|
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Stage: 90.93 (Confirmed)
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