This standard has been revised by: ISO/IEC TR 14496-9:2009
The main goal of ISO/IEC TR 14496-9:2008 is to facilitate a more widespread use of the MPEG-4 standard.
Design methodologies of the EDA industry have evolved from schematics to Hardware Description Languages (HDLs) to address the needs of the vast number of gates available on a single device. The increased number of gates allowed more elaborate algorithms to be deployed but also required a shift in design paradigm to handle the complexity created. Through HDLs, more complicated systems could be designed faster through the enabling technology of synthesis of the HDL code towards different silicon technologies where trade offs could be explored. Now the EDA industry again faces challenges where HDLs may not provide the level of abstraction needed for system designers to evaluate system level parameters and complexity issues. There have been a number of tool investigations under way to address this problem. Profiling tools aid in exposing bottlenecks in an abstract way so that early design decisions can be made. C to gates tools allow a C based simulation environment while also enabling direct synthesis to gates for hardware acceleration.
In conclusion, it is the aim of this ISO/IEC TR 14496-9:2008 to enable more widespread use of the MPEG-4 standard through reference hardware descriptions and close integration with ISO/IEC TR 14496-7 (MPEG-4 Part 7 Optimized Reference Software). Additionally, it is aimed that exposure to such a platform will enable a more systematic way to investigate the complexity of new codecs and open up the algorithm search space with an order of magnitude more compute cycles.
Document published on: 2008-08-15 Edition: 2 (Monolingual) ICS: 35.040 Status: Withdrawn Stage: 95.99 (2009-01-20) TC/SC: ISO/IEC JTC 1/SC 29 Number of Pages:
Revised by: ISO/IEC TR 14496-9:2009
Revises: ISO/IEC TR 14496-9:2004